Peripherals Routed Through the DAI
A-184 ADSP-214xx SHARC Processor Hardware Reference
Sample Rate Converter Registers
The sample rate converter (SRC) is composed of five registers which are
described in the following sections.
Control Registers (SRCCTLx)
The SRCCTLn control registers (read/write) control the operating modes,
filters, and data formats used in the sample rate converter. For n = 0, the
register controls the SRC0 and SRC1 modules and for n = 1 it controls the
SRC2 and SRC3 modules (x = 0, 2 and y = 1, 3). The bit settings for these
registers are shown in Figure A-98 and described in Table A-96.
7–4 FIFO_RDI Read Index Pointer. Reflects the read index status during
core reads from the IDP_FIFO.
0000 = No read done
1000 = 8 reads done
31–8 Reserved
Table A-95. DAI_STAT1 Register Bit Descriptions (RO) (Cont’d)
Bit Name Description
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