ADSP-214xx SHARC Processor Hardware Reference A-55
Registers Reference
Control Status Register 0 (SDSTAT0)
The SDRAM control status register provides information on the state of
the SDC. This information can be used to determine when it is safe to
alter SDC control parameters or as a debug aid. This register is shown in
Figure A-24 and described in Table A-29.
22
(WO)
FMR Force Load Mode Register Command. This command performs a
load mode register command immediately.
0 = No effect
1 = Force MR
23 SDBUF Pipeline Option with External Register Buffer.
0 = No buffer option
1 = External SDRAM CTL/ADDR control buffer enable
26–24 SDTRCD SDRAM tRCD Specification. RAS to CAS Delay is = 1–7 SDCLK
cycles. Based on the system clock frequency and the timing specifica-
tions of the SDRAM used. Programmed parameters apply to all four
banks in the external memory.
See the SDRAM data sheet.
29–27 SDRAW Row Address Width.
000=8, 001=9
010=10, 011=11
100=12, 101=13
110=14, 111=15
30 PGSZ 128 Page Size of 128 Words. This bit allows programs to configure the
SDC for a page size of 128 words (7 bits) which supports most avail-
able 32 Mb SDRAMs.
0 = No effect, page size decided by SDCAW bits.
1 = Page size 128 words. Column width = 7 bits, override CAW set-
tings.
31 SDAD-
DRMODE
Select Address Mapping. This bit selects how data is stored in mem-
ory.
0 = Bank interleaving
1 = Page interleaving
Table A-28. SDCTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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