ADSP-214xx SHARC Processor Hardware Reference 22-11
Power Management
External Port Control
The EPOFF bit in the PMCTL1 register allows programs to disconnect the
clocks to the SDRAM and AMI modules in order to save power if the con-
trollers are not used. Note that if the SDRAM/DDR2 controller is used
but pauses, the self-refresh mode also helps to reduce power consumption.
For more information, see “SDRAM Controller
(ADSP-2147x/ADSP-2148x)” on page 3-17.
Disabling the SDRAM Controller
If the SDC is not used, the DSDCTL bit can be disabled to stop the clock
and reduce power dissipation.
The DSDCTL bit must be set (=1) in products without the SDRAM
interface to reduce power consumption. Set this bit as early as pos-
sible after booting the part.
Disabling the DDR2 Controller
If the DDR2 interface for ADSP-2146x processor is not used, the follow-
ing bits should be configured in order to provide maximum power
reduction.
•In the
DDR2CTL0 register, set (=1) the following bits: DIS_DDR2CTL,
DIS_DDR2CLK1 and DIS_DDR2CKE to disable the controller and its
I/O pads.
•In the
DDR2PADCTL0 register (bits 9, 19 and 29) and DDR2PADCTL1
register (bits 9 and 19), set (=1) all the
PWD bits (power-down
receiver pad).
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