ADSP-214xx SHARC Processor Hardware Reference A-269
Registers Reference
Peripheral Timer Registers
The timer peripheral module provides general-purpose timer functional-
ity. It consists of three identical timer units. Each timer has
memory-mapped registers. They are described in the following sections.
Read-Modify-Write Timer Control Register
For the Timer global control register, the traditional read-modify-write
operations to disable a timer have changed. The action is to directly write
which simplifies timer enable/disable and can be accomplished with fewer
instructions. Example:
Instead of:
ustat3=dm(TMCTL); /* Timer Control Register */
bit set ustat3 TIM1DIS; /* disables timer 1 */
dm(TMCTL)=ustat3;
Use:
ustat3 = TIM1DIS;
dm(TMCTL)=ustat3;
Writes to the enable and disable bit-pair for a timer works as follows.
TIMxDIS = 0, TIMxEN = 0 – No action
TIMxDIS = 0, TIMxEN = 1 – Enable the timer
TIMxDIS = 1, TIMxEN = x – Disable the timer
For reads, the interpretation is as follows.
TIM1DIS = 0, TIMxEN = 0 – Timer is disabled
TIM1DIS = 1, TIMxEN = 1 – Timer is enabled
Any other read combination is not possible. Read of the TMCTL register
returns the enable status on both the enable and disable bits.
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