ADSP-214xx SHARC Processor Hardware Reference 20-17
UART Port Controller
For DMA, the transmit interrupt is generated when a DMA in transmit
mode is complete whereas the receive interrupt is generated when a receive
DMA is complete or when a receive error occurs. The
UARTRXSTAT register
reports whether the interrupt is due to DMA completion or errors.
For information on using the UART for DMA transfers, see “DMA
Transfers” on page 20-13, “Interrupts” on page 9-32, and Appendix B,
Peripheral Interrupt Control.
Core Interrupts
The UART has two interrupt outputs referred to as the UART RX and
UART TX interrupts. This is somewhat misleading in that in core mode
all interrupts are grouped together as a single interrupt (UART_RX).
Even though the UART has two interrupts for receive and trans-
mit, in core mode, all interrupts are grouped as a single receive
interrupt (UARTRXI) only.
The UART interrupt enable register (UARTIER) is used to enable requests
for core system handling of empty or full states of UART data registers.
Unless polling is used as a means of action, the UARTRBFIE and/or UARTT-
BEIE bits in this register are normally set.
Setting the bits of this register in core mode enables the UART to inter-
rupt the processor for each word of data. For proper operation in this
mode, system interrupts must be enabled, and appropriate interrupt han-
dling routines must be present. For backward compatibility, the
UARTIIR
register still reflects the correct interrupt status. The transmit interrupt
request is cleared by writing new data to the UARTTHR register or by reading
the UARTIIR register.
When the UARTTBEIE bit is set in the UARTIER register for core
transfers, the UART module immediately issues an interrupt.
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