Interrupts
20-18 ADSP-214xx SHARC Processor Hardware Reference
When initiating the transmission of a string, no special handling of the
first character is required. Set the
UARTTBEIE bit (bit 1) and let the inter-
rupt service routine (ISR) load the first character from memory and write
it to the UARTTHR register in the normal manner. Accordingly, the UARTT-
BEIE bit should be cleared if the string transmission has completed.
Alternatively, UART writes and reads can be accomplished by ISRs. Sepa-
rate interrupt lines are provided for the transmit, receive, and error
signals. The independent interrupts can be enabled individually by the
UARTIER register.
For legacy reasons, the UART interrupt identification register (UARTIIR)
still reflects the UART interrupt status (see Table 20-4). Legacy operation
may require bundling all UART interrupt sources to a single interrupt
channel and servicing them all by the same software routine. This can be
established by globally assigning all UART interrupts to the same inter-
rupt priority using the programmable interrupt priority control registers.
Please note the special role of the UARTIIR register read in the case where
the service routine does not want to transmit further data. If software
stops transmission, it must read the UARTIIR register to reset the interrupt
request. As long as the UARTIIR register reads 0x04 or 0x06 (indicating
that another interrupt of higher priority is pending), the UARTTHR empty
latch cannot be cleared by reading the UARTIIR register.
The following restrictions should be noted.
1. If either the line status interrupt or the receive data interrupt has
been assigned a lower interrupt priority by the interrupt controller,
a deadlock condition can occur. To avoid this, always assign the
lowest priority of the enabled UART interrupts to the UARTTHR
empty event.
2. Because of the destructive nature of reading the UARTIIR register, a
shadow register (UARTIIRSH) is provided for reading the contents of
the corresponding main register.
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