ADSP-214xx SHARC Processor Hardware Reference 9-39
Digital Application/Digital Peripheral Interfaces
latched in one of the
DAI_IMASK_x registers, all of them must be ser-
viced before executing an RTI instruction. For more information,
see “Interrupt Controller Registers” on page A-149.
DPI Interrupt Acknowledge
Any asynchronous or synchronous interrupt causes a latency, since it
forces the core to stop processing an instruction in process, then vector to
the interrupt service routine (ISR), (which is basically an interrupt vector
table (IVT) lookup), then proceed to implement the instruction refer-
enced in the IVT.
The DPI triggers one interrupt in the primary IVT.
When a DPI interrupt occurs, the DPI_IMASK register determines which of
the 12 interrupt sources requires service.
Reading the DPI’s interrupt latches (DPI_IMASK) clears the inter-
rupts (Read-to-Clear bit type). Therefore, the ISR must service all
the interrupt sources it discovers. That is, if multiple interrupts are
latched in one of the registers, all of them must be serviced before
executing an RTI instruction.
For UART and TWI interrupts in core operation, the interrupt acknowl-
edge mechanisms may be different. For more information, refer to the
specific chapters (Chapter 20, UART Port Controller, Chapter 21, Two
Wire Interface Controller).
Core versus DAI/DPI Interrupts
A pair of registers (DAI_IRPTL_H and DAI_IRPTL_L) replace functions nor-
mally performed by the
IRPTL register. A single register (DAI_IRPTL_PRI)
specifies to which latch these interrupts are mapped.
Two registers (
DAI_IMASK_RE and DAI_MASK_FE) replace the DAI periph-
eral’s version of the
IMASK register. As with the IMASK register, these DAI
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