Analog Devices SHARC ADSP-214 Series

ADSP-2147x, ADSP-2148x External Port Registers
A-58 ADSP-214xx SHARC Processor Hardware Reference
Refresh Rate Control Register (SDRRC)
The SDRAM refresh rate control register provides a flexible mechanism
for specifying the auto-refresh timing. The SDC provides a programmable
refresh counter which has a period based on the value programmed into
the
RDIV field of this register, that coordinates the supplied clock rate with
the SDRAM device’s required refresh rate. This register is shown in
Figure A-26. For information on using the
SMODIFY bit see “SDRAM Read
Optimization” on page 3-40.
23–16 External Bank 2
Status
External Bank 0 Active/Precharge State.
xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
…
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
31–24 External Bank 3
Status
External Bank 0 Active/Precharge State.
xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
…
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
Table A-30. SDSTAT1 Register Bit Descriptions (RO) (Cont’d)
Bit Field Field Name Description
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