ADSP-214xx SHARC Processor Hardware Reference 2-3
I/O Processor
Register Overview
Two global IOP registers control the DMA arbitration over the I/O
buses—the first for the peripheral bus and the second for the external port
bus. This section provides brief descriptions of the major IOP registers.
For complete information, see “Register Listing” on page A-273.
System Control Register (SYSCTL). Controls the peripheral DMA oper-
ation for fixed or rotating DMA channel arbitration.
External Port Control Register (EPCTL). Controls the external port
DMA operation for fixed or rotating DMA channel arbitration and
between the core and DMA.
DMA Channel Registers
The following sections provide information on the registers that control
all DMA operations for each peripheral. Additional information on DMA
operations can be found in specific peripheral chapters.
DMA Channel Allocation
Each channel has a set of parameter registers which are used to set up
DMA transfers. Table 2-28 on page 2-36 shows the DMA channel alloca-
tion and parameter register assignments for the ADSP-214xx processors.
DMA channels vary by processor model. For a breakdown of DMA
channels for a particular model, see the product specific data sheet.
Also note that each DMA channel has a specific peripheral assigned
to it.
To Next Page
Loading...
Need help?
General
