Operating Modes
11-12 ADSP-214xx SHARC Processor Hardware Reference
Packing by 3
Packing by 3 packs three acquired samples together. Since the resulting
32-bit word is not divisible by three, up to ten bits are acquired on the
first clock edge and up to eleven bits are acquired on each of the second
and third clock edges:
• On clock edge 1, bits 19–10 are moved to bits 9–0 (10 bits)
• On clock edge 2, bits 19–9 are moved to bits 20–10 (11 bits)
• On clock edge 3, bits 19–9 are moved to bits 31–21 (11 bits)
This mode sends one packed 32-bit word to FIFO for every three input
clock cycles—the DMA transfer rate is one-third the PDAP input clock
rate.
Figure 11-4. PDAP Hold Input (Packing by 2)
PDAP_CLK_I
PDAP DATA
PDAP_HOLD_I
W0 W1 W0
W1
W0
W0 W1 W0
W1
PDAP_STROBE_O
PDAP_CLK_I
PDAP DATA
PDAP_HOLD_I
PDAP_STROBE_O
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