ADSP-214xx SHARC Processor Hardware Reference 11-27
Input Data Port
Setting Miscellaneous Bits
This sequence is used in most following programming models as interme-
diate step.
Set the required values for:
•
IDP_SMODEx bits in the IDP_CTLx register to specify the frame sync
format for the serial inputs (left-justified I
2
S, or right-justified
mode).
• IDP_Pxx_PDAPMASK bits in the IDP_PP_CTL register to specify the
input mask, if the PDAP is used.
• IDP_PP_SELECT bits in the IDP_PP_CTL register to specify input from
the DAI pins or the DATA pins, if the PDAP is used.
• IDP_PDAP_CLKEDGE bit (bit 29) in the IDP_PP_CTL register to specify
if data is latched on the rising or falling clock edge, if the PDAP is
used.
Starting Core Interrupt-Driven Transfer
To start a core interrupt-driven data transfer:
1. Clear the FIFO by setting (= 1) IDP_FFCLR bit (bit 31 in the
IDP_CTL1 register).
2. Keep the SCLK and frame sync inputs of the SIP and PDAP con-
nected to low, by setting the proper values in the SRU registers.
3. Refer to “Setting Miscellaneous Bits” above.
4. Program the SRU registers to establish the proper connection to
the SIP and/or PDAP being used. Keep the unused clock and frame
sync signals connected to low.
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