Programming Model
4-24 ADSP-214xx SHARC Processor Hardware Reference
Receive DMA
The following is the sequence that occurs when an external device trans-
fers a block of data into the processor’s internal memory using a link port.
Note that the link ports do not support internal to internal mem-
ory transfers like previous SHARCs. If internal to internal memory
transfers are required, refer to “External Port DMA” on page 3-65.
1. The processor writes the DMA channel’s parameter registers (index
register IILBx, modify register IMLBx and count register CLBx) and
initializes the link port for receive (LTRAN = 0).
2. The processor enables the link port by setting the LEN bit. DMA is
enabled by setting the LDEN bit in the LCTLx register.
3. The external device begins writing data to the RXLBx buffer through
the link port.
4. The RXLBx buffer detects that data is present and sends a internal
DMA request.
5. After the request is granted, the DMA transfer is performed
thereby emptying the RXLBx buffer FIFO.
Transmit DMA
The following is the sequence that occurs when the processor transfers a
block of data from its internal memory to an external device using link
port.
1. The processor writes the DMA channel’s parameter registers (index
register
IILBx, modify register IMLBx and count register CLBx) and
initializes the link port for transmit (
LTRAN = 1).
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