IIR Accelerator
6-70 ADSP-214xx SHARC Processor Hardware Reference
5. Set the
IIR_ADRINC bit in IIRDEBUGCTL register for address auto
increment.
6. Write start address to the IIRDBGADDR register. If bit 11 is set, coef-
ficient memory is selected.
7. Wait at least 4 CCLK cycles.
8. Write data to the IIRDBGWRDATA_L register.
9. Write data to the IIRDBGWRDATA_H register.
Reading from Local Memory
1. Enable IIR module in PMCTL1 register.
2. Wait at least 4 CCLK cycles.
3. Clear the IIR_DMAEN bit in the IIRCTL1 register.
4. Set the IIR_DBGMODE, IIR_DBGMEM and IIR_HLD bits in the
IIRDEBUGCTL register.
5. Set the IIR_ADRINC bit in the IIRDEBUGCTL register for address auto
increment.
6. Write start address to the IIRDBGADDR register. If bit 11 is set, coef-
ficient memory is selected.
7. Wait at least 4 CCLK cycles.
8. Read data from the IIRDBGRDDATA_L register.
9. Read data from the
IIRDBGRDDATA_H register.
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