ADSP-214xx SHARC Processor Hardware Reference 20-9
UART Port Controller
transmitter transmits the
TX9D bit instead of the parity bit. During 9-bit
transmission mode, the parity select controls and the word length select do
not have any effect.
For the receiver, set the RX9 bit in the UART_MODE register and the UAEN bit
in the UAC_RXCTL register (to enable reception). Set the address enable bit
(UARTAEN) to enable address detection.
If the received ninth bit is high, the received word is shifted from the RSR
register to the UART_RBR buffer which generates an interrupt. Read the
UART_RBR buffer to find out if the device is being addressed. If the device is
being addressed, the address enable (UARTAEN bit) is cleared to allow data
and address bytes to be read into the receive buffer.
During the 9 bit transmission mode parity has to be calculated in software
to detect errors. The reception may be stopped when the receiver receives
another address which is different from its own.
In 9-bit mode, the address detect interrupt can be generated whenever the
receiver gets an address word, irrespective of the packing mode. This helps
programs respond to an address word immediately. The program is
expected to take into account these features when using packed mode.
Packed Mode
Programs must use care when using the packing feature in 9-bit
transmission mode.
• Programs should write the UARTPKSYN bit (bit 1) with a 1 each time
an address is received. This starts the reception of the following
data from the lower half-word of the UARTRBR register.
• The address-detect interrupt is generated whenever the UART
receiver receives an address, irrespective of the packing. The DR bit
in the UARTLSR register can be used to discover whether the address
is in the lower (
DR = 0) or higher half-word (DR = 1). The LSR reg-
ister must be read before reading the
UARTRBR register, because the
To Next Page
Loading...
Need help?
General
