Programming Model
15-34 ADSP-214xx SHARC Processor Hardware Reference
receive DMA the status bit is asserted when the DMA count becomes
zero. For transmit DMA the
SPIFE goes high when:
• the DMA count becomes zero and
• the DMA FIFO becomes empty and
•the SPITX buffer becomes empty (TXS bit high) and
• transfer is complete (SPIF bit goes high)
Note that the SPIFE bit can go high between two DMA blocks of a
chained DMA.
Switching From Transmit to a New DMA
The following sequence details the steps for switching from transmit to
transmit/receive DMA.
With SPI disabled:
1. Poll the SPIFE bit in the SPISTAT register. If this bit is high the SPI
can be disabled.
2. Clear the SPICTLx register to disable the SPI. Disabling the SPI also
clears the RXSPIx/TXSPIx buffer and the buffer status.
3. Disable DMA by clearing the
SPIDMACx register.
4. Clear all errors by writing to the W1C-type bits in the SPISTATx
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
5. Reconfigure the SPICTLx register and enable the SPI ports.
6. Configure DMA by writing to the DMA parameter registers and
the
SPIDMACx registers using the SPIDEN bit (bit 0).
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