ADSP-214xx SHARC Processor Hardware Reference A-83
Registers Reference
FIR MAC Status Register (FIRMACSTAT)
This register, shown in Figure A-37 and described in Table A-49, provides
the status of MAC operations. The status of all four multipliers/adders are
available separately for programs to poll. In fixed-point mode only the
ARIx bits are used (all other bits are reserved).
Figure A-37. FIRMACSTAT Register
Table A-49. FIRMACSTAT Register Bit Descriptions (RO)
Bits Name Description
0FIR_MACMRZ0Multiplier Result Zero. Set if multiplier 0 results is zero.
1 FIR_MACMRI0 Multiplier Result Infinity. Set if multiplier 0 results is infinity.
2FIR_MACMINV0Multiply Invalid. Set if multiplier 0 multiply operation is
invalid.
3FIR_MACARZ0Adder Result Zero. Set if a adder 0 results is zero.
4FIR_MACARI0Adder Result Infinity. Set if adder 0 results is infinity. Indi-
cates overflow in fixed-point mode.
5 FIR_MACAINV0 Addition Invalid. Set if a adder 0 addition is invalid.
FIR_MACAINV1
FIR_MACARZ2
FIR_MACMRZ3
FIR_MACAINV2
FIR_MACARI2
FIR_MACMINV2
FIR_MACMRI2
FIR_MACMRZ2
FIR_MACMRZ0
FIR_MACMRI0
FIR_MACMINV0
FIR_MACARZ0
FIR_MACARI0
FIR_MACAINV0
FIR_MACARI1
FIR_MACARZ1
FIR_MACMINV1
FIR_MACMRZ1
FIR_MACMRI1
FIR_MACAINV3
FIR_MACARI3
FIR_MACARZ3
FIR_MACMINV3
FIR_MACMRI3
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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