Operation Modes
7-24 ADSP-214xx SHARC Processor Hardware Reference
in each half period (or 2 x
PCLK for the full period). In double update
mode, improved accuracy is possible since different values of the duty
cycles registers are used to define the on times in both the first and second
halves of the PWM period. As a result, it is possible to adjust the on-time
over the whole period in increments of PCLK. This corresponds to an
effective PWM accuracy of PCLK in double update mode (or 10 ns for a
200 MHz clock). The achievable PWM switching frequency at a given
PWM accuracy is tabulated in Table 7-4. In Table 7-4, PCLK = 200 MHz.
Synchronization of PWM Groups
The PWMGCTL register enables or disables the four PWM groups in any
combination. This provides synchronization across the four PWM groups.
The
PWM_SYNC_ENx bits in this register can be used to start the counter
without enabling the outputs through
PWM_EN. So when PWM_ENx is
asserted, the 4 PWM outputs are automatically synced to the initially pro-
grammed period. In most cases, all SYNC bits can be initialized to zero,
enabling the PWM_ENx bits of the four PWM groups at the same time syn-
chronizes the four groups.
Table 7-4. PWM Accuracy in Single- and Double Update Modes
Resolution (bits) Single Update Mode PWM
Frequency (kHz)
Double Update Mode PWM Frequency
(kHz)
8
200 MHz ÷ 2
× 2
8
= 390.63 200 MHz ÷ 2
8
= 781.25
9 195.3 390.6
10 97.7 195.3
11 48.8 97.7
12 24.4 48.8
13 12.2 24.4
14 6.1 12.2
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