ADSP-214xx SHARC Processor Hardware Reference I-7
Index
DMA (continued)
channels, 2-2
circular buffered, 2-8, 2-24
configuring in the I/O processor, 2-51
control/status registers, 2-36
data buffer, 2-32, 2-36
direction change (external port), 2-23
extended parameter registers, 2-8
external port bus, 2-43
external port bus priority, A-20, A-46
FFT chaining, 2-18
handshake, 2-30
IIR chaining, 2-17
index addresses, 2-27
index registers, 2-4
interrputs, 2-45 to 2-48
interrupt sources, FIR, 6-45, 6-65
loading chain, 2-34
miscellaneous external port parameter
registers, 2-9
offset value, 2-27
operation, master mode, 15-31, 15-33
parameter registers, 2-36
ping-pong, 2-23, 2-24
ping-pong, IDP, 11-21
ping-pong enable (IDP_PING) bits,
A-178
program controlled interrupt (PCI) bit,
2-12, 2-13, 6-18, 10-48, 15-13,
20-22, A-167
read optimization example, 3-43, 3-78
rotating peripheral priority, 2-44
slave, interrupts, 4-19
SPI slave mode, 15-31, 15-32
SPORT chain status bits (DMACHSxy),
A-171
SPORT status bit (DMASxy), A-171
standard (non chained), 2-23
starting/stopping, 2-29
DMA
(continued)
switching from receive
to transmit mode,
15-35
switching from transmit to receive mode,
15-34
TCB, 2-21, 2-32
TCB allocation, 2-32
TCB size, 2-32
transfer control block See DMA
TCB
transfer direction, external port, 2-24
transfers, 11-20
DMACx (external port DMA registers),
A-60
DMA example, chain assignment, 2-34
Dolby, DTS audio standards (S/PDIF),
13-13
DPI
connections, group A, A-218 to A-222
connections, group B, A-223 to A-226
connections, group C, A-226 to A-230
pin assignment (group B) signals, A-223
pin enable (group C) signals, A-226
DSP, architectural overview, 1-2
DSxEN (SPI device select) bits, 15-31,
15-33, A-242
DTS format, 13-17
DTYPE, 10-22
DTYPE (data type) bits, A-153, A-163
DXS_B, DSX_A (data buffer channel A/B
status) bit, A-157, A-158, A-161,
A-166
E
early vs. late frame syncs, 10-27
edge-related interrupts, 9-37
ELSI (enable RX status interrupt) bit,
A-247
emergency dead time example, 7-16
To Next Page
Loading...
