DMA Channel Registers
2-12 ADSP-214xx SHARC Processor Hardware Reference
For the new SPORT external memory functionality, when writing
tests which involve the PCI bit, the external memory address should
be split before writing to the chain pointer register.
Note that the serial ports have the ability to fetch TCBs from external
memory.
Table 2-10. Chain Pointer Register (CPx)
Bit Name Description
18–0 IIx address Next chain pointer address
19 PCI Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
Table 2-11. SPORT Chain Pointer Register (CPSPx)
Bit Name Description
18–0 IIx address Next chain pointer address (bits 18–0 of
the chain pointer)
19 PCI Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
27–20 IIx address Next chain pointer (external address,
bits 27–19 of the chain pointer)
Table 2-12. External Port Chain Pointer Register (EPCPx)
Bit Name Description
18–0 IIx address Next chain pointer address
19 PCI Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
20 CPDR DMA direction for next TCB
0 = write to internal memory
1 = read from internal memory
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