ADSP-214xx SHARC Processor Hardware Reference 11-29
Input Data Port
3. Wait for the DAI interrupt, and enable the IDP port inside the
DAI interrupt service routine.
4. Clear the DAI interrupt by reading the DAI interrupt latch regis-
ter. This procedure ensures that the IDP ports are enabled at the
correct time, avoiding issues like channel shift or swap in the
received data.
Starting A Standard DMA Transfer
To start a DMA transfer from the FIFO to memory:
1. Clear the FIFO by setting (= 1) the IDP_FFCLR bit (bit 31 in the
IDP_CTL1 register).
2. While the global IDP_DMA_EN and the IDP_EN bits are cleared (= 0),
set the values for the DMA parameter registers that correspond to
channels 7–0.
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the SRU
registers.
4. Refer to “Setting Miscellaneous Bits” above.
5. Route all of the required inputs to the IDP by writing to the SRU
registers
6. Enable the channel’s IDP_ENx and IDP_DMA_ENx bit settings.
7. Start the DMA by setting
• The
IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register if the
PDAP is required).
• The global IDP_DMA_EN bit of the IDP_CTL0 register to enable
standard DMA on the selected channel.
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