Operating Modes
20-8 ADSP-214xx SHARC Processor Hardware Reference
Operating Modes
The two UART operation modes are described in the following sections.
Data Packing
The UART provides packed and unpacked modes of data transfer to and
from the internal memory of the processors. This mode is set using the
UARTPACK bit (bit 0) in the UARTMODE register. In unpacked mode, the data
word is appended to the left with 24 zeros during transmission or recep-
tion. In packed mode, two words of data are transmitted or received with
their corresponding higher bytes filled with zeros. For example, consecu-
tive data words 0xAB and 0xCD are packed as 0x00CD 00AB in the
receiver, and 0x00CD 00AB is transmitted as two words of 0xAB and
0xCD successively from the transmitter. Packing is available in both I/O
and DMA modes. A control bit, UARTPKSYN, can be used to re synchronize
the packing. For information on using the UART for DMA transfers, see
“DMA Transfers” on page 20-13.
The packed feature is provided to use the internal memory of the
processor in a more efficient manner.
Note that in packed mode, both the transmitter and receiver operate with
an even number of words. A transmit-buffer-empty or receive-buffer-full
interrupt is generated only after an even number of words are transferred.
Programs must use care when using the packing feature in 9-bit
mode.
9-Bit Transmission Mode
To select 9-bit transmission mode in the transmitter, set the TX9 bit in the
UART_MODE register and the UAEN bit in the UART_TXCTL register (to enable
transmission). The 9-bit data (TX9D) can be directly written to the
UART_THR buffer – either in packed or unpacked format. The UART
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