Programming Models
3-128 ADSP-214xx SHARC Processor Hardware Reference
4. Self refresh mode-no activities on all SDRAM signals (clock
optional).
5. Clear the
DSDCTL bit to re-enable SDCLK (optional).
6. SDRAM access releases controller from self-refresh mode.
Changing the VCO Clock During Runtime
In previous SHARC models, only a hardware reset initiated another
SDRAM power-up sequence. This is no longer the case since the PLL
allows programs to change the output clocks during runtime.
All SDRAM timing specifications are normalized to the SDRAM clock.
Since most of these are minimum specifications, (except t
REF
, which is a
maximum specification), a variation of the system clock violates a specific
specification and causes a performance degradation for the other
specifications.
The reduction of the system clock violates the minimum specifications,
while increasing the system clock violates the maximum t
REF
specification. Therefore, careful software control is required to adapt these
changes. Therefore, the release from self-refresh mode should be a dummy
read operation since it happens with the old frequency settings.
For most applications, the SDRAM power-up sequence and writ-
ing of the mode register needs to occur only once. Once the
power-up sequence has completed, the
SDPSS bit should not be set
again unless a change to the mode register is desired.
The recommended procedure for changing the system frequency SDCLK is
as follows.
1. Set the SDRAM to self-refresh mode by writing a 1 to the
SDSRF bit
of the
SDCTL register.
2. Poll the
SDSRA bit of SDSTAT register for self-refresh grant.
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