S/PDIF Receiver
13-18 ADSP-214xx SHARC Processor Hardware Reference
Single-Channel Double-Frequency Mode
Single-channel, double-frequency mode (SCDF) mode is selected with
DIR_SCDF and DIR_SCDF_LR bits in the DIRCTL register. The DIR_B0CHANL/R
bits in the DIRSTAT register also contain information about the SCDF
mode. When the DIR_B0CHANL/R indicates single channel double frequency
mode, the two subframes of a frame carry successive audio samples of the
same signal. Bits 0–3 of channel status byte 1 are decoded by the receiver
to determine one of the following:
• 0111 = single channel double frequency mode
• 1000 = single channel double frequency mode–stereo left
• 1001 = single channel double frequency mode–stereo right
Clock Recovery Modes
The S/PDIF receiver extracts audio data, channel status, and user bits
from the biphase encoded AES3 and S/PDIF stream. In addition, a 50%
duty cycle reference clock running at the sampling rate of the audio input
data is generated for the PLL in the receiver to recover the oversampling
clock.
Digital On-Chip PLL
The receiver can recover the clock from the biphase encoded stream using
an on-chip digital PLL shown in Figure 13-8. Note the dedicated on-chip
digital PLL is separate from the PLL that supplies the clock to the SHARC
processor core and which is the default operation of the receiver.
The left/right frame reference clock for the PLL is generated using the pre-
ambles. The recovered low jitter left/right frame clock from the PLL
attempts to align with the reference clock. However, this recovered
left/right clock, like the reference clock, is not phase aligned with the
preambles.
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