ADSP-214xx SHARC Processor Hardware Reference 6-15
FFT/FIR/IIR Hardware Modules
Inverse FFT
The inverse FFT uses the same algorithm as the forward FFT. The acceler-
ator takes advantage of this fact when processing IFFTs by setting up a
coefficient TCB with change of sign for the sine twiddles (FFT uses twid-
dles cosine, sine, -sine, cosine, the IFFT uses cosine, -sine, sine, cosine).
When TCB loading completes, the accelerator processes the inverse FFT
and returns the data into the local data memory. Finally, in write mode,
data is returned to internal memory.
In order to get the correct amplitude for the inverse FFT, the output buf-
fer needs to be scaled by 1/N.
Data Transfer
The FFT accelerator works exclusively through DMA and therefore does
not require core intervention. This allows the core to perform other sys-
tem tasks. The core is used to configure the DMA parameter registers and
the accelerator control registers and to start accelerator operation.
FFT Buffers
As shown in Figure 6-1 on page 6-3, the input and output DMA stream
each pass an 8 deep buffer. These I/O buffers ensure that the FFT stream
of the accelerator is not stalled during high DMA bus loads. Note that the
buffer status cannot be read.
DMA Transfers
The FFT accelerator supports circular buffer chained DMA. Two TCB
structures are associated with input and output DMA. The input TCB
structure is used for transferring either data or coefficients to the accelera-
tor block and the output TCB is used for receiving data from the FFT
block to the internal memory of the SHARC processor. For TCB struc-
ture details see “FFT Accelerator TCB” on page 2-18.
To Next Page
Loading...
Need help?
General
