IIR Accelerator
6-64 ADSP-214xx SHARC Processor Hardware Reference
Accelerator input and output channels are used to connect to internal
memory.
Note that the IIRCTL2 register is part of the IIR TCB. This allows
to program individual IIR channels having different control
attributes.
Interrupts
The IIR accelerator has two interrupts that are programmable through the
PICR registers ( Appendix B, Peripheral Interrupt Control). The ACC0I and
ACC1I source bits are used to connect IIR interrupts to the peripheral
interrupt inputs of the core.
One interrupt line is shared by all the DMA interrupts and the other by
MAC status interrupts. Separate status registers are provided to further
differentiate the various sources.
Interrupt Sources
There are two interrupt sources associated with the accelerator. The
IIR_CCINTR bit in the IIRCTL1 register controls these interrupts. When set,
the bit generates window complete interrupt and when cleared (default),
an interrupt is generated after all the channels are complete.
Window Complete Interrupt – This interrupt is generated at the end of
each channel when all the output samples are calculated corresponding to
a window and updated index values are written back.
Table 6-4. Overview of IIR Interrupts
Interrupt Source Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
IIR (2 channels) - Window Complete
- Channel Complete
- MAC status
- Internal trans-
fer completion
RTI instruction Need to route
ACCxI (PICRx)
to any PxxI
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