ADSP-214xx SHARC Processor Hardware Reference 11-31
Input Data Port
Servicing Interrupts for DMA
The following steps describe how to handle an IDP ISR for DMA.
1. An interrupt is generated and program control jumps to the ISR
when the DMA for a channel completes.
2. The program clears the
IDP_DMA_EN bit in the IDP_CTL register.
a. To ensure that the DMA of a particular IDP channel is
complete, (all data is transferred into internal memory) wait
until the
IDP_DMAx_STAT bit of that channel becomes zero in
the DAI_STAT register. This is required if a high priority
DMA (for example a SPORT DMA) is occurring at the
same time as the IDP DMA.
b. As each DMA channel completes, a corresponding bit in
either the DAI_IMASK_L or DAI_IMASK_H register for each
DMA channel is set (IDP_DMAx_INT).
3. The program clears (= 0) the channel's IDP_DMA_ENx bit in the
IDP_CTL1 register which has finished.
4. Reprogram the DMA registers for finished DMA channels.
More than one DMA channel may have completed during this
time period. For each, a bit is latched in the DAI_IMASK_L or
DAI_IMASK_H registers. Ensure that the DMA registers are repro-
grammed. If any of the channels are not used, then its clock and
frame sync should be held LOW.
5. Read the DAI_IMASK_L or DAI_IMASK_H registers to see if more inter-
rupts have been generated.
• If the value(s) are not zero, repeat step 4.
• If the value(s) are zero, continue to step 6.
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