Analog Devices SHARC ADSP-214 Series

ADSP-214xx SHARC Processor Hardware Reference A-39
Registers Reference
Controller Status Register 1 (DDR2STAT1)
This register reports the DDR2 bank active/idle status. This register is
shown in Figure A-15 and described in Table A-19.
Figure A-15. DDR2STAT1 Register
Table A-19. DDR2STAT1 Register Bit Descriptions (RO)
Bit Field Field Name Description
7–0 External Bank 0
Status
External Bank 0 Active/Precharge State.
xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
…
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
15–8 External Bank 1
Status
External Bank 0 Active/Precharge State.
xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
…
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
Bit Field (23–16)
External Bank 2
Status
Bit Field (31–24)
Bit Field (7–0)
Bit Field (15–8)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
098 37564 2114 12 11 101315
External Bank 0
Status
External Bank 1
Status
External Bank 3
Status
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