High Frequency Design
23-36 ADSP-214xx SHARC Processor Hardware Reference
Asynchronous Inputs
The processor has several asynchronous inputs such as
IRQ2-0, FLAG3–0,
ACK and the DAI/DPI pins and reset inputs RESET, TRST, running reset
which can be asserted in arbitrary phase to the reference clocks. The pro-
cessor synchronizes the reset inputs to the CLKIN input while the
peripheral inputs are synchronized to the PCLK prior to recognizing them.
The delay associated with recognition is called the synchronization delay.
Any asynchronous input must be valid prior to the recognition point in a
particular cycle. If an input does not meet the setup time on a given cycle,
it may be recognized in the current cycle or during the next cycle.
To ensure recognition of an asynchronous input, it must be asserted for at
least one PCLK cycle plus setup and hold time, except for RESET, which
must be asserted for at least four CLKIN processor cycles. The minimum
time prior to recognition (the setup and hold time) is specified in the
appropriate product data sheet.
Decoupling and Grounding
Designs should use an absolute minimum of four bulk capacitors
(2 × 10 µF for VDDINT and 2 × 10 µF for V
DDEXT
). Furthermore a mini-
mum of 20 × 10nF ceramic bypass capacitors (5 per chip corner for
V
DDINT
and V
DDEXT
).
Capacitors type, value and placement is critical—especially for floating
point computations, which draw more power. If the bulk/bypass capaci-
tors are insufficient, the power rails may drop, causing errors. Therefore
sufficient capacitor backup is important.
To Next Page
Loading...
Need help?
General
