ADSP-214xx SHARC Processor Hardware Reference 3-95
External Port
Instruction Cache
To circumvent the relative difference in clock domains between the core
and external memory interface (1:2 in the best case) and enable faster exe-
cution throughput, the functionality of the traditional “conflict” cache on
the SHARC has been enhanced to serve as an instruction cache in external
execution mode.
In previous generations of SHARC processors, the function of the conflict
cache had been to cache only those instructions whose fetching conflicted
with access of a data operand from memory over the PM bus. The
enhancements to the cache architecture mean that the functionality of the
cache remains intact for execution from internal memory whereas it
behaves as instruction cache for external memory execution.
Every instruction that is fetched from external memory into the
program sequencer is also simultaneously loaded into the cache.
The next time that this instruction needs to be fetched from external
memory, it is first searched for in the cache. The instruction is stored
using the entire 24-bit address. Figure 3-19 shows the format for storing
an instruction.
0x20 0001 0x30 0002 Instr/Fetch1 [47:16]
0x30 0003 Instr/Fetch2 [31:0]
0x20 0002 0x30 0004 Instr/Fetch3 [15:0] Instr/Fetch2 [47:32]
0x30 0005 Instr/Fetch3 [47:16]
Table 3-23. Booting Instructions Into External Memory
Sequencer Feych
Address
Normal Word
Address
Normal Word Data
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