ADSP-214xx SHARC Processor Hardware Reference 6-7
FFT/FIR/IIR Hardware Modules
Resetting via a logic low to the
RESET pin resets all registers, thereby clear-
ing the FFT_RST bit. Once the processor is brought out of reset by applying
a logic high to the RESET pin, the FFT module goes into the idle state in
the next clock cycle.
Idle State
This mode is used to program the accelerator’s control registers. Setting
the FFT_EN and FFT_START bits in the FFTCTL1 register moves the state
from idle to reading.
Read State
In this state the module reads data and coefficients, but counts the num-
ber of read data only. This is because for successive FFT calculations the
coefficient need not be read again—only the next set of data has to be
read. When a specified number of data words are read, the state automati-
cally moves to processing.
Processing State
In this mode the module computes FFT ping-pong stages in memory.
Once this is done, the state automatically moves to the write state.
Write State
In this mode all the computed data is written out to internal memory. The
state then automatically changes to either idle or read, depending on the
way the block is configured using the repeat function (
FFT_RPT bit in the
FFTCTL2 register). If the FFT_RPT bit is set, the block moves to the read
state, if cleared, the block moves to the idle state. The
FFT_RPT bit is useful
when programs need to continuously perform an FFT on input data with-
out core intervention.
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