Peripheral Registers
A-76 ADSP-214xx SHARC Processor Hardware Reference
Control Register (FFTCTL2)
The FFT control register, shown in Figure A-34 and described in
Table A-43, is used to set up individual FFT parameters (such as length)
and how the module process the FFT, such as data packing.
6 FFT_DBG Debug Mode Enable.
0 = Disable
1 = Enable
31–7 Reserved
Figure A-34. FFTCTL2 Register
Table A-42. FFTCTL1 Register Bit Descriptions (RW) (Cont’d)
Bits Name Description
VDIM (11–7)
FFT_RPT
FFT_CPACKIN
Complex Word Input Packing
(<512 words)
Accelerator Repeat
FFT_CPACKOUT
Complex Word Output Packing
(<512 words)
FFT_LOG2VDIM (6–3)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
FFT_LOG2HDIM (15–12)
HDIM (20–16)
NOVER256 (28–21)
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