ADSP-214xx SHARC Processor Hardware Reference 19-7
WatchDog Timer – ADSP-2147x
Debug Features
The following section provides information on debugging features avail-
able with the watchdog timer.
Emulation Considerations
An emulation halt stops the WDT counter. The WDT resumes counting
after being released from emulation halt. Single stepping is not supported
for WDT in emulation mode.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Watchdog Timers Effect Latency
After the WDT registers are configured the effect latency is 2 PCLK cycles
enable and 2
PCLK cycles disable.
Programming Model
If enabled, the 32-bit watchdog timer counts downward every WDT_CLKIN
cycle. When it becomes 0, the system is reset. The counter value can be
read through the 32-bit
WDTCURCNT register. The WDTCURCNT register can-
not, however, be written directly. Rather, software writes the watchdog
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