Programming Model
19-8 ADSP-214xx SHARC Processor Hardware Reference
period value into the 32-bit
WDTCNT register before the watchdog is
enabled. Once the watchdog is started, the period value cannot be altered.
To start the watchdog timer:
1. Unlock the WDT configuration registers by writing the unlock
“command” value to the WDTUNLOCK register. Select the WDTCLK by
programming the WDTCLKSEL bit.
By Default, the resonator output is WDTCLK.
2. Set the trip counter value for the watchdog timer by writing to the
WDTTRIP register.
3. Set the count value for the watchdog timer by writing the count
value into the watchdog period register (WDTCNT). Since the watch-
dog timer is not yet enabled, the write to the WDTCNT registers
automatically pre-loads the WDTCURCNT register as well. Note that
sufficient time must be provided for the write to the WDTCURCNT reg-
ister to occur (2.5 WDTCLK cycles max.), before enabling WDT.
4. Enable the watchdog timer in WDTCTL.
5. Lock the WDT configuration registers by writing to the WDTUNLOCK
register. The watchdog timer begins counting down, decrementing
the value in the WDTCURCNT register every WDT_CLKIN cycle. If soft-
ware does not serve the watchdog in time, WDTCURCNT continues
decrementing until it reaches 0 and the system is reset.
The counter now reloads the
WDTCURCNT value from WDTCNT and
keeps decrementing. Additionally, the WDRO latch bit in the WDT-
STATUS
register is set and can be interrogated by software. This
occurs up to the number of times programmed in the
WDTTRIP reg-
ister. When WDTTRIP expires, WDT holds the WDTRSTO asserted.
6. To prevent the watchdog from expiring, software serves the watch-
dog by unlocking the WDT configuration space and performing
dummy writes to the
WDTCURCNT register address in time. The values
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