Analog Devices SHARC ADSP-214 Series - Input Data Format

ADSP-214xx SHARC Processor Hardware Reference 13-9
Sony/Philips Digital Interface
24-bit word widths. The over sampling clock is also selected by the trans-
mitter control register.
Input Data Format
The Figure 13-3 through Figure 13-7 shows the format of data that is sent
to the S/PDIF transmitter using a variety of interfaces.
Figure 13-2. AES3 Output Block
Figure 13-3. Data Packing for I
2
S and Left-Justified Format
7
LRCLK
24
3
24
3
BLK_START
M_COUNT
BIPHASE_TX_CLK
FREQMULT
2
SAMPLE
LR
BIPHASE
ENCODER
TX_CLK_GEN_SYNC
TX_ENABLE
SAMPLE BIT
U, V, CS BITS
BIPHASE_CLK
LEFT DATA
RIGHT DATA
U, V, CS RIGHT
U, V, CS LEFT
BIPHASE_OUT
DAI
BLK_START_O
EXT SYNC
STATUS/USER
BIT REGISTERS
INTERNAL
BUFFER
Bits 31–8: 24-Bit Audio Data 7654BITS 3–0
Padding (zero)
Block Start
Channel Status
User Data
Validity Bit
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