Data Transfer
3-94 ADSP-214xx SHARC Processor Hardware Reference
Table 3-22 provides addressing for various sizes of SDRAM memory.
Writing Instructions to External Memory
As described in the previous sections, the sequencer fetches instructions
from physical 16-bit addresses, regardless of whether they are ISA or
VISA instructions. However, to boot instructions into external memory
via core or DMA, normal word space is required. Since the memory space
is aliased the short word address space is accessible in normal word space,
which is a right shift of the short word address (0x60 0000 >>1 is 0x30
0000).
As shown in Table 3-23, instructions are stored in an interleaved fashion
which ensures that the memory is used efficiently. For every 2 fetches
(VISA) or instructions (ISA) 3 memory accesses are required. For more
information refer to the Visual DSP tools loader file documentation.
Table 3-22. Translation of Logical to Physical Addressing for SDRAM
DDR2 Device Physical Address Range Mapped to
Memory Device
Mapping Between External Port
Address Range and Memory Device
32 Mb (x16) 0x60 0000 – 0x7F FFFF 0x00 0000 – 0x1F FFFF
64 Mb (x16) 0x60 0000 – 0x9F FFFF 0x020 0000 – 0x3F FFFF
0x000 0000 – 0x1F FFFF
128 Mb (x16) 0x60 0000 – 0xDF FFFF 0x020 0000 – 0x7F FFFF
0x000 0000 – 0x1F FFFF
256 Mb (x16) 0x60 0000 – 0x15F FFFF 0x020 0000 – 0xFF FFFF
0x000 0000 – 0x1F FFFF
Table 3-23. Booting Instructions Into External Memory
Sequencer Feych
Address
Normal Word
Address
Normal Word Data
0x20 0000 0x30 0000 Instr/Fetch 0 [31:0]
0x30 0001 Instr/Fetch1 [15:0] Instr/Fetch0 [47:32]
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