Analog Devices SHARC ADSP-214 Series - Mute Register (SRCMUTE); Ratio Registers (SRCRATx)

ADSP-214xx SHARC Processor Hardware Reference A-189
Registers Reference
Mute Register (SRCMUTE)
This register connects an SRCx mute input and output when the
SRC0_MUTE_ENx bit is cleared (=0). This allows SRCx to automatically
mute input while the SRC is initializing (0 = automatic muting and
1 = manual muting). Bit 0 controls SRC0, bit 1 controls SRC1, bit 2 con-
trols SRC2, and bit 3 controls SRC3.
Ratio Registers (SRCRATx)
These registers report the mute and I/O sample ratio as follows: the
SRCRAT0 register reports for SRC0 and SRC1 and the SRCRAT1 register
reports the mute and I/O sample ratio for SRC2 and SRC3 (X = SRC0
and SRC1, Y = SRC2 and SRC3). The registers are shown in Figure A-99
and Figure A-100 and described in Table A-97.
30 Reserved
31 SRCy_ENABLE SRC Enable. Enables SRC 1, 3. When (set = 1), or when the
sample rate (frame sync) between the input and output changes,
the SRC begins its initialization routine where;
1) MUTE_OUT is asserted,
2) soft mute control counter for input samples is set to maxi-
mum attenuation (–144 dB).
Note that SRC power-up completion is finished by clearing the
SRCx_MUTEOUT bit in SRCRATx register. Writes to the
SRCCTLx register should be at least one cycle before setting the
SRCx_ENABLE. When setting and clearing this bit, it should
be held low for a minimum of 5 PCLK cycles. Programs should
disable the SRC when changing modes.
Table A-96. SRCCTLx Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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