ADSP-214xx SHARC Processor Hardware Reference 6-53
FFT/FIR/IIR Hardware Modules
6. Write start address to the
FIRDBGADDR register. Note if bit 11 is set,
coefficient memory is selected.
7. Wait at least 4 CCLK cycles.
8. Read data from the FIRDBGRDDATA register.
Single Step Mode
Single step mode can be used for debug purposes. An additional debug
register is used in this mode.
1. Enable stop DMA during breakpoint hit in the emulator settings.
2. Clear the FIR_HLD bit and enable FIR_DBGMODE and FIR_RUN bits in
FIRDEBUGCTL register.
3. Program FIR module according to the application.
4. In single step each iteration is updated in the emulator session.
FIR Programming Example
An application needs FIR filtering of six channels of data. The first four
channels require 256 TAP filtering and the last two channels require 1024
TAP filtering. The window size for all the channels is 128.
1. Create a circular data buffer in internal memory for each channel.
The buffer should be large enough to avoid overwriting data before
being processed by the accelerator. Ideally, the input buffer size for
a channel is tap length + window size – 1 for that channel. The 256
coefficients of each of the first four channels and the 1024 coeffi-
cients each of the last two channels are also configured in internal
memory buffers. The output buffer size is equal to the window size.
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