ADSP-214xx SHARC Processor Hardware Reference 14-11
Precision Clock Generator
Timing Example for I2S Mode
For I
2
S mode, the frame sync should be driven at the falling edge of SCLK.
In other words, the frame sync edge should coincide with the falling edge
of the SCLK. To satisfy this requirement, the phase of the frame sync
should be programmed accordingly in the PCG_CTLxx registers.
For example, assume that the input clock source for both clock and frame
sync are the same and both the clock and frame sync are enabled at the
same time. Also assume that the clock divisor value needed to generate the
required SCLK is CLKDIV = 4. Then, for a 32-bit word length, the frame
sync divisor value should be FSDIV = 64 × CLKDIV = 256.
By default, for phase = 0, the rising edge of both SCLK and frame sync will
coincide. To make sure that the frame sync edges coincides with the fall-
ing edge of the SCLK, the phase value needs to be programmed as
CLKDIV/2 = 2. It can be done by following instructions:
ustat1=CLKDIV|((CLKDIV/2) << 20);
dm(PCG_CTLx1) = ustat1;
For details on how to program phase of the frame sync see “Programming
Model” on page 14-20.
Operating Modes
The following sections provide information on the operating modes of the
precision clock generator.
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