FIR Accelerator
6-48 ADSP-214xx SHARC Processor Hardware Reference
Additional Information
It may be difficult to achieve the required performance by using sample
based processing (Window size = 1). Increasing the window size provides
more computation time and the ability to perform the real time process-
ing. It is a common practice to use block based processing (Window size
greater 1).
In the following example,the core is running at 450 MHz with a single
channel tap length of 512. Sampling frequency = 96 kHz and the maxi-
mum processing time is 10 µs.
The computation of the filter requires:
TCB load + 4 × N + W(N/4 + 2)) × C.
For window size = 1
49 + 4 × 512 + 1 × (512/4 + 2) = 2227
PCLK = 9.8 us.
For window size = 10
49 + 4 × 512 + 10 × (512/4 + 2) = 3397 PCLK = 15 us.
Therefore, 10 samples at 96 kHz = 10 x 10 = 100 us of available process-
ing time: Actual time used is 15 us.
Programming Model
The following steps should be used when programming the accelerator.
Enable the FIR accelerator by setting accelerator select bits (ACCSEL in the
PMCTL1 register) to 00.
Single Channel Processing
1. Create input, coefficient, and output buffers in internal memory.
For input and coefficient buffer storage format see “Coefficients
and Input Buffer Storage” on page 6-35.
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