DDR2 DRAM Controller (ADSP-2146x)
3-54 ADSP-214xx SHARC Processor Hardware Reference
different internal banks. For 8 banked devices, the controller does follow
the t
FAW
specification.
Precharge
This command is executed by the controller if the address to be accessed
falls in a different page in the same external bank and the same internal
bank. A precharge is not done if the address to be accessed falls in an open
page in another internal or external bank.
For page miss reads or writes, only the external and internal banks to be
accessed by the read or write is pre-charged. For auto-refresh and
self-refresh, all external DDR2 banks are pre-charged at one time.
Precharge All
This command is given to precharge all internal banks. Just before an auto
refresh or self refresh, or during the power up sequence, the controller
always issues the precharge command to all internal DDR2 banks. For
eight bank devices, the t
FAW
period must be satisfied while performing the
precharge all command.
Burst Read
The burst read command is initiated by having DDR2_CS and DDR2_CAS low
while holding DDR2_RAS and DDR2_WE high at the rising edge of the clock.
The address inputs determine the starting column address for the burst.
The delay from the start of the command to when the data from the first
cell appears on the outputs is equal to the value of the read latency (RL).
The data strobe output (
DDR2_DQS) is driven low one clock cycle before
valid data (DDR2_DATA) is driven onto the data bus (Figure 3-12). The first
bit of the burst is synchronized with the rising edge of the data strobe
(DDR2_DQS).
Each subsequent data-out appears on the DDR2_DATA The first bit of the
burst is synchronized with the rising edge of the data strobe (
DDR2_DQS).
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