Features
16-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The peripheral timers have the features described below.
• Independent general-purpose timers
• Three operation modes (PWM, Width capture, external watchdog)
• Global control/status registers for synchronous operation of multi-
ple timers
• Buffered timer registers (Period and Width) to allow changes on
the fly
The core timer is controlled by system registers while the periph-
eral timers are controlled by memory-mapped registers.
DMA Chaining N/A
Interrupt Source Core
Boot Capable N/A
Local Memory No
Clock Operation f
PCLK
Table 16-1. Timer Specifications (Cont’d)
Feature Timer1–0
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