ADSP-214xx SHARC Processor Hardware Reference A-35
Registers Reference
DDR2 Control Register 4 (DDR2CTL4)
The
DDR2CTL4 register includes the programmable parameters associated
with the DDR2 extended mode register 2 (EMR2). Table A-15 shows the
DDR2 control register bit definition. All the values are defined in terms of
number of clock cycles. Values written into this register are loaded into
the DDR2 extended mode register 3 during power up (or when the force
EMR bit in the
DDR2CTL0 register is set). This register should be initialized
before starting the initialization sequence.
This register’s contents should not be changed while DDR2 inter-
face is active. Also whenever this register contents are changed an
initialization sequence must be executed to reflect this register con-
tents in to the DDR2 extended mode register 3.
DDR2 Control Register 5 (DDR2CTL5)
The
DDR2CTL5 register includes the programmable parameters associated
with the DDR2 extended mode register 3 (EMR3).Table A-16 shows the
DDR2 control register bit definition. All the values are defined in terms of
number of clock cycles. Values written into this register are loaded into
the
DDR2EMR2 register during power up (or when the Force EMR bit in
DDR2CTL0 is set). This register should be initialized before starting the ini-
tialization sequence.
Table A-15. DDR2CTL4 Register Bit Descriptions (RW)
Bit Name Description
13–0 Reserved.
15–14 DDR2EXTMR2 Extended Mode Register 2.
Must be set to 10.
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