ADSP-214xx SHARC Processor Hardware Reference A-91
Registers Reference
IIR MAC Status Register (IIRMACSTAT)
The
IIRMACSTAT register, shown in Figure A-42 and described in
Table A-54, provides the status of MAC operations.
IIR DMA Status Register (IIRDMASTAT)
The IIR DMA registers are described in “Data Transfer” on page 6-15.
The
IIRDMASTAT register, shown in Figure A-43 and described in
Table A-55, provides the status of DMA operations. All the bits in this
register are read only.
Figure A-42. IIRMACSTAT Register
Table A-54. IIRMACSTAT Register Bit Descriptions (RO)
Bits Name Description
0IIR_MRZMultiplier Result Zero. Set if multiplier results is zero.
1IIR_MRIMultiplier Result Infinity. Set if multiplier results is infinity.
2 IIR_MINV Multiply Invalid. Set if multiply operation is invalid.
3IIR_ARZAdder Result Zero. Set if adder results is zero.
4IIR_ARIAdder Result Infinity. Set if adder results is infinity.
5IIR_AINVAddition Invalid. Set if addition is invalid.
31–6 Reserved
IIR_MRZ
IIR_MRI
IIR_MINV
IIR_AINV
IIR_ARI
IIR_ARZ
09 837564 2114 12 11 101315
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