Peripheral Registers
A-92 ADSP-214xx SHARC Processor Hardware Reference
Figure A-43. IIRDMASTAT Register
Table A-55. IIRDMASTAT Register Bit Descriptions (RO)
Bits Name Description
0 IIR_DMACPL Chain Pointer Loading Status.
1 = state machine in chain pointer load state
1 IIR_DMACnDkLD Coefficient and Dk Loading.
2 IIR_DMAPPGS MAC Processing In Progress.
3 IIR_DMAWRBK Writing Back Updated Index Registers.
4 IIR_DMASVDk Saving Updated Dk State in Internal Memory.
5 (ROC) IIR_DMAWDONE Processing of Current Channel Done. Sticky, cleared on
register read.
6 (ROC) IIR_DMAACDONE All Channels Done. Sticky, cleared on register read.
11–7 IIR_DMACURCHNL Current Channel. Channel that is being processed in the
TDM slot. Zero indicates the last slot.
31–12 Reserved
IIR_DMACPL
Chain Pointer Load Status
IIR_DMAURCHNL (11–7)
Current Channel
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
IIR_DMACNDKLD
Coefficient Loading
IIR_DMAACDONE
All Channels Done
IIR_DMAPPGS
MAC Processing in
Process
IIR_DMAWDONE
Processing of Current Channel Done
IIR_DMAWRBK
Write Back Updated
Index Pointers
IIR_DMASVDK
Saving Updated Dk State in Internal
Memory
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