ADSP-214xx SHARC Processor Hardware Reference 3-127
External Port
Output Clock Generator Programming Model
The following non VCO programming sequence may be used to change
the output generator clock and the core-to-peripheral clock ratio (for
example the SDRAM clock). Note that if your program is only changing
the PLL output divider, programs do not need to wait 4096
CLKIN cycles
(required only if the PLL multiplier or the INDIV bit is modified).
1. Disable the peripheral (SDRAM). Note that the peripherals cannot
be enabled when changing clock ratio.
2. Select the PLL divider by setting the PLLDx bits (bits 6–7 in the
PMCTL register).
3. Select the clock divider (CCLK to SDRAM ratio) by setting the ratio
bits (PMCTL register).
4. Wait 15 CCLK cycles. During this time, programs must not execute
any valid instructions.
5. Enable the peripheral (SDRAM).
The new divisor ratios are picked up on the fly and the clocks
smoothly transition to their new values after a maximum of 15 core
clock CCLK cycles.
Self-Refresh Mode
The following steps are required when enter and releasing self-refresh
mode.
1. Set the SDSRF bit to enter self-refresh mode.
2. Poll the
SDSRA bit in the SDRAM status register (SDSTAT) to deter-
mine if the SDRAM has already entered self-refresh mode.
3. Set the
DSDCTL bit to freeze SDCLK (optional).
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