ADSP-214xx SHARC Processor Hardware Reference 13-11
Sony/Philips Digital Interface
Operating Modes
The S/PDIF transmitter can operate in standalone and full serial modes.
The following sections describe these modes in detail.
Full Serial Mode
This mode is selected by clearing bit 9 in the DITCTL register. In this mode
all the status bits, audio data and the block start bit (indicating start of a
frame), come through the serial data stream (DIT_DATA_I) pin. The trans-
mitter should be enabled after or at the same time as all of the other
control bits.
Standalone Mode
This mode is selected by setting bit 9 in the DITCTL register. In this mode,
the block start bit (indicating the start of a frame) is generated internally.
The channel status bits come from the channel status buffer registers
(DITCHANAx and DITCHANBx). The user status bits come from the user bits
buffers (DITUSRBITAx and DITUSRBITBx) as shown in Figure 13-2 on
page 13-9.
The channel status buffer must be programmed before the S/PDIF
transmitter is enabled and used for all the successive blocks of data.
The validity bit for channel A and B are taken from bit 10 and bit 11 of
the DITCTL register. In this mode only audio data comes from the
DIT_DATA_I pin. All other data, including the status bit and block start bit
is either generated internally or taken from the internal register.
Once the user bits buffer registers (DITUSRBITA0-5 and DITUSRBITB0-5) are
programmed, they are used only for the next block of data. This allows
programs to change the user bit information in every block of data.
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