External Port DMA
3-106 ADSP-214xx SHARC Processor Hardware Reference
If chaining is enabled with the OFCEN bit set then the TRAN bit has
no effect, and direction is determined by the CPDR bit in the CPEP
register.
Scatter/Gather DMA
The purpose of scatter/gather DMA (Table 3-26, Figure 3-24 through
Figure 3-27) is the transfer of data from/to non contiguous memory
blocks.
The scatter/gather DMA type is a fixed block size scatter/gather DMA
that relies on tap list entries in internal memory to calculate the external
address to scatter/gather the DMA. If the DMA direction is external write
(TRAN = 1) then it is a scatter DMA. If TRAN = 0 then it is a gather DMA.
This mode also supports chained and circular buffer chained DMAs.
External Address Calculation
For scatter/gather DMA, the tap list modifiers are employed and the num-
ber of taps is determined by the tap list count register (
TCEPx). The
number of sequential reads (block size) from every tap is determined by
Table 3-26. External Read/Write Index Calculation
Scatter/Gather DMA
Equation Result
EIEP + TL[N] First address for tap N
EIEP + TL[N] + 1 × EMEP
Second address for tap N
EIEP + TL[N] + 2 × EMEP
Third address for tap N
...
EIEP + TL[N] + ICEP
× EMEP
Final address for tap N
EIEP + TL[N + 1] First address for tap N + 1
EIEP + TL[N + 1] + 1
× EMEP
Second address for tap N + 1
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