ADSP-214xx SHARC Processor Hardware Reference 3-105
External Port
Bit 20 (
CPDR) bit of the external port chain pointer register (CPEPx)
changes the data flow direction. If CPDR is cleared (=0) writes to internal
memory are performed, if CPDR is set (=1), internal memory reads are per-
formed. This works similar to the PCI bit (bit 19). Bit 8 (OFCEN) and bit 2
(CHEN) in the DMACx register must be set (=1) to enable this functionality.
Listing 3-7. Changing DMA Direction
.section/pm seg_dmda;
/* EP TCB storage order CP-EM-EI-C-IM-II */
.var TCB1[6] = 0 , M , extbuffer , N , M , buffer;
.var TCB2[6] = 0 , M , extbuffer , N , M , buffer;
.section/pm seg_pmco;
R0=0;
dm(CPEP0)=R0; /* clear CPx register */
r0 = DEN|CHEN|OFCEN; /* enable DMA channel */
dm(DMAC0)=r0;
R2=(TCB1+5) & 0x7FFFF; /* load IIx address of next TCB and
mask address */
R2=bset R2 by 19; /* set PCI bit */
dm(TCB2)=R2; /* write address to CPx location of
current TCB */
R2=(TCB2+5) & 0x7FFFF; /* load IIx address of next TCB and
mask address*/
R2=bset R2 by 19; /* clear PCI bit */
R2=bset R2 by 20; /* set CPDR bit */
dm(TCB1)=R2; /* write address to CPx location of
current TCB */
dm(CPEP0)=R2; /* write IIx address of TCB1 to CPx
register to start chaining*/
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