ADSP-214xx SHARC Processor Hardware Reference 3-41
External Port
(bits 20–17) in the
SDRRC register according to the core’s DAG modifier or
the DMA’s modify parameter register.
The predictive address given to the memory depends on the SDMODIFY bit
values. For example, if the DAG modifier = 2, the SDMODIFY value should
also be 2, in which case the address + 2 is the predictive value provided to
the SDRAM address pins. Programs may choose to determine whether
read optimization is used or not. If read optimization is disabled, then
each read takes 7 cycles for a CAS latency of 3, even for sequential reads.
With read optimization enabled, 32 sequential reads, with offsets ranging
from 0 to 15, take only 37 SDCLK cycles. Read optimization should not be
enabled while reading at the external bank boundaries. For example, if
SDMODIFY = 1, then 32 locations in the boundary of the external banks
should not be used. These locations can be used without optimization
enabled. If SDMODIFY = 2, then 64 locations cannot be used at the bound-
aries of the external bank (if it is fully populated).
It is advisable to use read optimization for core and DMA, with a constant
modifier to achieve better performance. With multiple channels running
with ping-pong accesses, use arbitration freezing to get better throughput.
By default, the read optimization is enabled (SDROPT = 1) with a
modifier of 1 (SDMODIFY = 1). Read optimization assumes that the
SDRAM pointer has a constant modifier. For non-sequential
accesses, turning off optimization provides better results.
Core Accesses
Any break of sequential reads of full page accesses can cause a throughput
loss due to a maximum of four extra reads (eight 16-bit reads). Listing 3-1
shows how to achieve maximum throughput using core accesses. Any cycle
between consecutive reads to an SDRAM address results in non-sequential
reads.
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