Analog Devices SHARC ADSP-214 Series - Page 172

SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-42 ADSP-214xx SHARC Processor Hardware Reference
Listing 3-1. Maximum Throughput Using Sequential Reads
ustat1=dm(SDCTL);
bit set ustat1 SDROPT|SDMODIFY1;
dm(SDCTL)=ustat1;
nop;
I0 = sdram_addr;
M0 = 1;
Lcntr = 512, do(PC,1) until lce;
R0 = R0 + R1, R0 = dm (I0, M0);
The example shows read optimization can be used efficiently using core
accesses. All reads are on the same page and it takes 1184 cycles to perform
512 reads.
Without read optimization, 512 reads use 6144 processor cycles if all of
the reads are on the same page. With read optimization (Listing 3-2), 512
reads take 7168 cycles, due to the breaking of sequential reads.
Listing 3-2. Interrupted Reads With Read Optimization
ustat1=dm(SDCTL);
bit set ustat1 SDROPT|SDMODIFY2;
dm(SDCTL)=ustat1;
nop;
I0 = sdram_addr;
M0 = 2;
Lcntr = 512, do(PC,2) until lce;
R0 = R0 + R1, R0 = dm (I0, M0);
NOP;
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